The present invention relates generally to the reduction or elimination of deleterious metal bridges and line shorts in interconnects in microminiaturized integrated circuits and more specifically to methods for the reduction of theta phase copper (CuAl2) growth in copper doped aluminum interconnects in microminiaturized integrated circuits in semiconductor devices.
Aluminum-based alloy films have been widely used as wiring materials of semiconductor devices. At first, non-doped aluminum films alone had been used. As integrated circuits became smaller and smaller, aluminum silicon (Alxe2x80x94Si) alloy films began to be used to deal with the problem of so-called alloy spike phenomenon. With semiconductor patterns becoming finer, the current density for wirings increased and electromigration become an important reliability problem. This phenomenon accompanied Si precipitation, micro-void growth and the like which the Alxe2x80x94Si alloy films/wirings were unable to handle.
Therefore, Alxe2x80x94Cu alloy films were introduced. Alxe2x80x94Cu alloy films are generally deposited by sputtering the metals on a semiconductor substrate. As deposited, the alloy is not a uniform solid solution with Al and Cu evenly distributed on the wafer substrate. Cu tends to react with Al to form theta phase copper, or CuAl2, nodular collections. The theta phase copper (CuAl2) would precipitate at the grain boundaries thus blocking mass transport of Al by the current which favorably reduced Al electromigration. Additional elements may form a part of the Alxe2x80x94Cu alloy containing metal, for example Alxe2x80x94Sixe2x80x94Cu alloys.
It is expected that as the temperature is elevated, Cu will travel, or diffuse through the Al lattice and seek out precipitates where it would chemically bond with Al atoms and cause the CuAl2 precipitate to grow. The Cu in the CuAl2 precipitate is in a lower energy state than the Cu in the solid solution alloy (bulk Al lattice) and thus the Cu tends to be bound in the theta phase rather than remain in the Al lattice. However, as wiring widths now approach grain size, the larger CuAl2 grain growth is more difficult to etch and may, among other things, lead to metal bridges and line shorts between adjacent interconnects or metal lines decreasing reliability.
U.S. Pat. No. 5,300,307 to Frear et al. describes a process for forming Alxe2x80x94Cu conductive thin films having reduced electromigration failures including the heat treatment or annealing of the thin film conductor at a temperature between 200 and 300xc2x0 C. for between 10 minutes and 24 hours under a reducing atmosphere such as 15% H2 in N2 by volume. This creates CuAl2 grain growth at the Alxe2x80x94Cu alloy grain boundaries.
U.S. Pat. No. 5,565,380 to Nemoto et al. describes a process for fabricating a semiconductor device having an interconnecting line formed of aluminum containing a predetermined additive element, such as Cu, wherein a segregate layer of the additive element is formed along aluminum grain boundaries in the interconnecting line on the basis of a heat treatment after the formation of the interconnecting line.
U.S. Pat. No. 5,238,874 to Yamada describes a laminated film consisting of an Alxe2x80x94Sixe2x80x94Cu alloy film and a refractory metal silicide film that includes Cu to reduce its electromigration while maintaining its good stressmigration characteristics. When the refractory metal silicide film is a tungsten silicide film, the Cu concentration is from 0.1 to 1.0 wt. %.
U.S. Pat. No. 5,318,923 to Park describes a method of forming a metal layer in a semiconductor device having a first process for depositing a metal at an optional temperature after forming the pattern of a contact hole, and a second process for annealing the deposited metal in a sputtering reaction chamber to fill up the contact with the metal.
U.S. Pat. No. 5,801,098 to Fiordalice et al. describes a method of decreasing resistivity in an electrically conductive layer using a high density plasma sputtering technique to deposit the electrically conductive layer over the substrate.
U.S. Pat. No. 5,665,641 to Shen et al. describes a process for forming a hard mask over an aluminum-containing layer for patterning and etching the aluminum-containing layer to define interconnects. The material comprising the hard mask is deposited at a temperature between about 100xc2x0 C. below the sputtering temperature of the aluminum-containing metal.
U.S. Pat. No. 5,288,665 to Nulman describes a process for forming an aluminum plug in a via in an insulating layer in an integrated circuit structure by first depositing a layer of aluminum over the insulating layer in a multistep deposition which will also result in filling the via with aluminum to form an aluminum plug, followed by removal of any additional aluminum formed over the surface of the insulating layer, and subsequent formation of one or more patterned conductive layers over the insulating surface which is in electrical communication with the underlying aluminum plug or via.
U.S. Pat. No. 5,141,896 to Katoh describes forming an inter-level insulating film at solid crossing points between upper level interconnections and lower-level interconnections, excepting via hole portions, in an semiconductor device. This provides mechanical support between interconnection levels and provides semiconductor devices having high durabilities against thermal and mechanical impacts.
Accordingly, it is an object of the present invention to provide improved methods of forming Alxe2x80x94Cu alloy containing metal interconnects.
Another object of the present invention is to provide improved methods of eliminated or reducing metal bridges and line shorts between interconnects or metal lines in semiconductor devices.
A further object of the present invention is to provide an improved method of forming Alxe2x80x94Cu alloy containing metal interconnects by sputtering an Alxe2x80x94Cu alloy containing metal layer followed by immediate cooling to minimize the growth of CuAl2 grains.
Yet another object of the present invention is to provide an improved method of forming Alxe2x80x94Cu alloy containing metal interconnects by sputtering an Alxe2x80x94Cu alloy containing metal layer, further processing of the semiconductor structure, then heating the semiconductor structure followed by prompt rapid cooling to minimize the growth of CuAl2 grains.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, in the first option of the present invention a semiconductor structure is provided and an overlying titanium nitride barrier layer is deposited thereon at about 100xc2x0 C. The semiconductor structure is loaded into a sputtering chamber and at least Al and Cu is sputtered over the titanium nitride barrier layer at about 270 to 300xc2x0 C. to form an Alxe2x80x94Cu alloy containing metal layer. The semi-conductor structure is then immediately transferred from the sputtering chamber into a cooling chamber and the sputtered Alxe2x80x94Cu alloy containing metal layer is cooled at a cooling rate greater than about 100xc2x0 C./minute to a temperature below 200xc2x0 C. to form a Alxe2x80x94Cu alloy containing metal layer having minimal CuAl2 grain growth. The semiconductor structure is removed from the cooling chamber and the semiconductor structure is processed further below 200xc2x0 C. to form semiconductor device precursors. The Alxe2x80x94Cu alloy containing metal layer is then patterned to form Alxe2x80x94Cu alloy containing metal lines and processing of the semiconductor structure is completed to form semiconductor devices having greater reliability due to the minimal CuAl2 grain growth.
In the second option of the present invention, a semiconductor structure having an overlying barrier layer is provided. At least Al and Cu is sputtered over the barrier layer at a first temperature to form an Alxe2x80x94Cu alloy containing metal layer having CuAl2 grains of a first average size. The semiconductor structure is processed, for example by the formation of ARC (anti-reflective coating) and BARC (bottom ARC) layers, and then heated to a second temperature to dissolve the CuAl2 grains of a first average size then rapidly cooling to a third temperature whereby the CuAl2 grains formed have a second average size within the Alxe2x80x94Cu alloy containing metal layer. The second average size CuAl2 grains being less than the first average size CuAl2 grains. The semiconductor structure is completed to form semiconductor devices having greater reliability due to the decreased second average size of CuAl2 grains.
The cooling rates for each above option are controlled by an argon (Ar) purge in chamber and a cooling water cooled wafer stage. Higher temperature wafers will generally have higher cooling rates.